Large computer systems commonly require clock signals to be distributed over long distances. This constitutes a significant engineering problem for clock signals at very high frequencies for which variations in propagation delays attributable, for example, to variations in the length of a clock signal conductor, can introduce skews in clocked events occurring at distant locations in the computer system.
One common technique to reducing clock skews in large computer systems is to introduce multiple clocks operating in separate clock domains of the system at substantially the same frequency. However, data which is transferred between separate clock domains requires synchronization with the clock in the receiving domain to preserve the clock-oriented integrity of the transferred data. Synchronization circuits for this purpose commonly involve phase-locked loops which link the sending and receiving clock domains to avoid latency or delays in transferring data between such domains. However, such phase-locked loops typically require incorporation of the clock oscillator within a feedback loop which frequently is not conveniently possible. In addition, phase-locked loops commonly operate at undesirably high levels of power dissipation. More importantly, where such clock domains communicate with several other clock domains, it is typically not possible to identify one clock to which all clock domains will synchronize.
Another conventional technique for synchronizing the transfer of data between clock domains uses a dual-port memory unit such as a first-in, first-out (FIFO) buffer which can be written to and read from at different time intervals, and at different frequencies. One disadvantage of such techniques is the latency or delay that is introduced into the communication of data between clock domains. In such techniques, the data (typically in a block or a frame) must be written or stored in the memory unit. A control signal typically must be propagated from the transmitting to the receiving domain to enable the read of data from the memory unit to the receiving domain.